Cell scaling is of critical importance to continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. Whilst classical transistor scaling has historically provided a key driver via contacted gate (poly) pitch (CPP) and metal layer (MX) pitch reduction, at aggressively scaled geometries, basic layout restrictions begin to fundamentally limit cell scaling. Such scaling is particularly challenging for SRAMs, even with the implementation of new device geometries. In particular, gate-all-around (GAA) architectures promise further CPP scaling; however using conventional constructs, SRAM scaling is impeded by ground rules requirements. One specific implementation of the GAA architecture is the VFET, where the current flows through a vertically-oriented channel; since this is a tremendous change in the fundamental device, new layout concepts are also required for standard cell designs. One known VFET SRAM design is shown in FIG. 1. Adverting to FIG. 1 (top view), the known design includes n-type active (nRX) regions 101 (bottom source/drain (S/D) regions) and p-type active (pRX) regions 103. The VFET SRAM also includes pulldown (PD) transistors 109 (connected to a source supply voltage (VSS)), pullup (PU) transistors 111 (connected to a drain supply voltage (VDD)), and pass gate (PG) transistors 113. The PD, PU, and PG transistors 109, 111, and 113, respectively, include fins 115, S/D contact regions (CA) 117, gates (PC) 119, gate contacts (CB) 121, and bottom S/D contacts (TS) 123. In addition, the S/D contact regions 117 of the PG gates 113 are connected to bit lines (BL) and the gate contacts 121 are connected to word lines (WL). However, this known SRAM architecture does not enable significant scaling of the bitcell area due to various contact and isolation requirements. Another known VFET SRAM design including an abutting active (RX) structure, which eliminates pRX-pRX space and aligns two PU transistors, is shown in FIG. 2. Adverting to FIG. 2, the abutting VFET SRAM design includes nRX regions 201 and pRX regions 203. Similar to the VFET SRAM of FIG. 1, the VFET SRAM of FIG. 2 also includes PD transistors 205 (connected to a VS S), PU transistors 207 (connected to a VDD), and PG transistors 209. The PD, PU, and PG transistors 205, 207, and 209, respectively, include fins 211, top contacts (not shown for illustrative convenience) connected to S/D contact regions 213, gates 215, gate contacts 217, and cross-couple (xc) contacts 219 connected to the bottom nRX regions 201 and pRX regions 203, in this case using bottom S/D contact metals strapped to gates 215. However, the bottom S/D xc contact requirements as drawn in this fashion, using the bottom S/D contact to strap the gate 215 metal to bottom nRX regions 201 and pRX regions 203, are subject to the contact-gate ground rule spacing requirements, which significantly increases the n-p space, thereby limiting the overall scaling.
A need therefore exists for methodology enabling formation of an interconnect to implement a xc connection that enables scaling of the bitcell area without increasing the n-p space and the resulting device.